FEATURES
s Fast Read Access Time: 70/90/120 ns s Low Power CMOS Dissipation: Licensed Intel second source s Commercial, Industrial and Automotive Temperature Ranges s On-Chip Address and Data Latches s JEDEC Standard Pinouts: –Active: 30 mA max (CMOS/TTL levels) –Standby: 1 mA max (TTL levels) –Standby: 100 µA max (CMOS levels) s High Speed Programming: –10 µs per byte –2 Sec Typ Chip Program –32-pin DIP –32-pin PLCC –32-pin TSOP (8 x 20) s 100,000 Program/Erase Cycles s 10 Year Data Retention s Electronic Signature s 0.5 Seconds Typical Chip-Erase s 12.0V ± 5% Programming and Erase Voltage s Stop Timer for Program/Erase DESCRIPTION
Electrical erasure of the full memory contents is achieved typically within 0.5 second. Programming and Erase are performed through an operation and verify algorithm. Address and Data are latched to free the I/O bus and address bus during the write operation. The CAT28F010 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 10 years.
Catalyst Semiconductor
