CAT28F010 Datasheet | Catalyst Semiconductor

FEATURES s Fast Read Access Time: 70/90/120 ns s Low Power CMOS Dissipation: Licensed Intel second source s mercial, Industrial and Automotive Temperature Ranges s On-Chip Address and Data Latches s JEDEC Standard Pinouts: - Active: 30 m A max (CMOS/TTL levels) - Standby: 1 m A max (TTL levels) - Standby: 100 µA max (CMOS levels) s High Speed Programming: - 10 µs per byte - 2 Sec Typ Chip Program - 32-pin DIP - 32-pin PLCC - 32-pin TSOP (8 x 20) s 100,000 Program/Erase Cycles s 10 Year Data Retention s Electronic Signature s 0.5 Seconds Typical Chip-Erase s 12.0V ± 5% Programming and Erase Voltage s Stop Timer for Program/Erase DESCRIPTION The CAT28F010 is a high speed 128K x 8-bit electrically erasable and reprogrammable Flash memory ideally suited for applications requiring in-system or after-sale code updates. Electrical erasure of the full memory contents is achieved typically within 0.5 second. It is pin and Read timing patible with standard EPROM and E2PROM devices. Programming and Erase are performed through an operation and verify algorithm. The instructions are input via the I/O bus, using a two write cycle scheme. Address and Data are latched to free the I/O bus and address bus during the write operation. The CAT28F010 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 10 years. The device is available in JEDEC approved 32-pin plastic DIP, 32-pin PLCC or 32-pin TSOP packages. I/O0- I/O7 BLOCK DIAGRAM I/O BUFFERS ERASE VOLTAGE SWITCH MAND REGISTER PROGRAM VOLTAGE SWITCH CE, OE LOGIC DATA LATCH SENSE AMP CE OE ADDRESS LATCH Y-GATING Y-DECODER 1,048,576 BIT MEMORY ARRAY 5108 FHD F02 A0- A16 X-DECODER VOLTAGE VERIFY SWITCH © 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Doc. No. 25005-0A 2/98 F-1 PIN CONFIGURATION DIP Package (P) VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS...