Pm25LD010 Datasheet | Chingis Technology

FEATURES - Single Power Supply Operation - Low voltage range: 2.3 V - 3.6 V - Memory Organization - Pm25LD512: 64K x 8 (512 Kbit) - Pm25LD010: 128K x 8 (1 Mbit) - Pm25LD020: 256K x 8 (2 Mbit) - Cost Effective Sector/Block Architecture - 512Kb : Uniform 4KByte sectors / Two uniform 32KByte blocks - 1Mb : Uniform 4KByte sectors / Four uniform 32KByte blocks - 2Mb : Uniform 4KByte sectors / Four uniform 64KByte blocks - Low standby current 1u A (Typ) - Serial Peripheral Interface (SPI) patible - Supports single- or dual-output - Supports SPI Modes 0 and 3 - Maximum 33 MHz clock rate for normal read - Maximum 100 MHz clock rate for fast read - Page Program (up to 256 Bytes) Operation - Typical 2 ms per page program - Sector, Block or Chip Erase Operation - Maximum 10 ms sector, block or chip erase - Low Power Consumption - Typical 10 m A active read current - Typical 15 m A program/erase current - Hardware Write Protection - Protect and unprotect the device from write operation by Write Protect (WP#) Pin - Software Write Protection - The Block Protect (BP2, BP1, BP0) bits allow partial or entire memory to be configured as readonly - High Product Endurance - Guaranteed 200,000 program/erase cycles per single sector - Minimum 20 years data retention - Industrial Standard Pin-out and Package - 8-pin 150mil SOIC - 8-pin 208mil SOIC for Pm25LD040 - 8-pin 300mil PDIP for Pm25LD040 - 8-contact WSON - 8-pin TSSOP - Lead-free (Pb-free), halogen-free package GENERAL...