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CX50561 - (CX5000 Series) Structured ASIC

This page provides the datasheet information for the CX50561, a member of the CX5000 (CX5000 Series) Structured ASIC family.

Description

The 0.18um CX5000 is an ASIC that utilizes the combination of an advanced metal programmable gate array and optimized EDA system to implement high performance ASIC designs while reducing application tooling costs and design turnaround time.

Features

  • Structured ASIC architecture Low NRE and start-up costs Fast time to production 30K to 1.2M usable ASIC gates Up to 2.6M bits of fast block memory w w w a D . S a t 2ns access time single-port SRAM, dual-port SRAM and ROM e e h U 4 t m o . c Low power consumption (0.06uW/MHz/Gate) 200MHz general core logic operation, 650MHz in constrained clock domains 1 CEC034 (9/20/05) © ChipX Inc. www. DataSheet4U. com C.

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Datasheet preview – CX50561

Datasheet Details

Part number CX50561
Manufacturer Chip Express
File Size 115.92 KB
Description (CX5000 Series) Structured ASIC
Datasheet download datasheet CX50561 Datasheet
Additional preview pages of the CX50561 datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com DATASHEET CX5000 0.18um Structured ASIC Product Description The 0.18um CX5000 is an ASIC that utilizes the combination of an advanced metal programmable gate array and optimized EDA system to implement high performance ASIC designs while reducing application tooling costs and design turnaround time. ASIC designers using the CX5000 are able to meet or exceed their design schedules and budgets without compromising technical objectives. The CX5000 comprises a family of pre-configured platform masterslices that contain varying amounts of general-purpose logic, fast memory, advanced I/Os, clock synthesis and phase management macrocells.
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