CH7517 Description
pliant with DisplayPort specification version 1.2 and Embedded DisplayPort (eDP) specification version 1.3. Support 2 Main Link Lanes at either 1.62Gb/s or 2.7Gb/s link rate Support analog RGB output for VGA with Triple 9-bit DAC up to 200MHz pixel rate. Sync signals can be provided in separated or posite manner.
CH7517 Key Features
- VGA output is pliant with VESA VSIS v1r2
- Embedded MCU to handle the control logic
- Support device boot up by automatically loading
- firmware from on-chip flash Boot ROM Integrated EDID Buffer, and MCCS bypass supported
- DAC connection detection supported
- DP input detection supported
- Support Auto Power Saving mode and low stand-by
- Support Spread Spectrum Clocking (de-spreading) for The DACs are based on current source architecture. And
- DP AUX channel and IIC slave interface are available With sophisticated MCU and the on-chip Flash, CH7517
- Low power architecture