CS2100-CP Overview
The CS2100-CP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2100-CP is based on a hybrid analog-digital PLL architecture prised of a unique bination of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digital PLL. This architecture allows for generation of a low-jitter clock relative to an external noisy synchronization clock at frequencies as low as 50 Hz.
CS2100-CP Key Features
- 75 MHz Clock from a Jittery or Intermittent 50 Hz to 30 MHz Clock Source Highly Accurate PLL Multiplication Factor
- Maximum Error Less Than 1 PPM in HighResolution Mode ® I²C / SPI™ Control Port Configurable Auxiliary Output Flexible So
- External Oscillator or Clock Source
- Supports Inexpensive Local Crystal Minimal Board Space Required
- No External Analog Loop-filter ponents
- 4 2. TYPICAL CONNECTION DIAGRAM
- 5 3. CHARACTERISTICS AND SPECIFICATIONS
- 6 REMENDED OPERATING CONDITIONS