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CS47024 - Audio SOC Processor

Download the CS47024 datasheet PDF. This datasheet also covers the CS470XX variant, as both devices belong to the same audio soc processor family and are provided as variant models within a single manufacturer datasheet.

General Description

CS470xx Data Sheet This document CS470xx Hardware User’s Manual Guide Includes detailed system design information such as typical connection diagrams, boot-procedures, and pin descriptions AN333 - CS470xx Firmware User’s Manual Includes a list of firmware modules available on the CS470xx family

Key Features

  • The CS470xx family is a new generation of audio system-on-a-chip (ASOC) processors targeted at high.
  • Cost-effective, High-performance 32-bit DSP fidelity, cost sensitive designs. Derived from the highly.
  • 300,000,000 MAC/S (multiply accumulates per second) successful CS48500 32-bit fixed-point audio enhancement processor family, the CS470xx further simplifies system.
  • Dual MAC cycles per clock design and reduces total system cost by integrating the S/.
  • 72-bit accumulato.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CS470XX-CirrusLogic.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Cirrus Logic

Part Number Description
CS47028 Audio SOC Processor
CS47048 Audio SOC Processor
CS47L15 Smart Codec
CS47L24 Low Power Audio Hub
CS47L35 Smart Codec

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CS470xx CS470xx Data Sheet Features The CS470xx family is a new generation of audio system-on-a-chip (ASOC) processors targeted at high  Cost-effective, High-performance 32-bit DSP fidelity, cost sensitive designs. Derived from the highly  300,000,000 MAC/S (multiply accumulates per second) successful CS48500 32-bit fixed-point audio enhancement processor family, the CS470xx further simplifies system  Dual MAC cycles per clock design and reduces total system cost by integrating the S/  72-bit accumulators are the highest precision in the industry  32K x 32-bit SRAM with three 2K blocks assignable to either Y data or program memory PDIF Rx, S/PDIF Tx, analog inputs, analog outputs, and SRCs.