CS5371 Description
z Fourth-order ∆Σ Architecture z Clock-jitter-tolerant Architecture z Input Voltage: 5 Vpp Fully Differential z High Dynamic Range 127 dB SNR @ 215 Hz BW (2 ms Output) 124 dB SNR @ 430 Hz BW (1 ms Output) z Low Total Harmonic Distortion -118 dB THD Typical, -112 dB THD Maximum z Low Power Consumption Normal Mode: 25 mW per Channel Low-power Mode:.