CS8422 Datasheet | Cirrus Logic

Features  140 d B Dynamic Range  -120 d B THD+N  No External Master Clock Required  Supports Sample Rates up to 211 k Hz  Input/Output Sample Rate Ratios from 6:1 to 1:6  Master Mode Master Clock/Sample Rate Ratio Support: 64, 96, 128, 192, 256, 384, 512, 768, 1024  16, 18, 20, or 24-bit Data I/O  Dither Automatically Applied and Scaled to Output Resolution  Multiple Device Outputs are Phase Matched Digital Audio Interface Receiver Features  plete EIAJ CP1201, IEC-60958, AES3, S/PDIF patible Receiver  28 k Hz to 216 k Hz Sample Rate Range  2:1 Differential AES3 or 4:1 S/PDIF Input Mux  De-emphasis Filtering for 32 k Hz, 44.1 k Hz, and 48 k Hz  Recovered Master Clock Output: 64 x Fs, 96 x Fs, 128 x Fs, 192 x Fs, 256 x Fs, 384 x Fs, 512 x Fs, 768 x Fs, 1024 x Fs  49.152 MHz Maximum Recovered Master Clock Frequency  Ultralow-jitter Clock Recovery  High Input Jitter Tolerance  No External PLL Filter ponents Required  Selectable and Automatic Clock Switching  AES3 Direct Output and AES3 TX Passthrough  On-chip Channel Status Data Buffering  Automatic Detection of pressed Audio Streams  Decodes CD Q Sub-Code SDIN ISCLK ILRCK RX0/RXP0 RX1/RXN0 RX2/RXP1 RX3/RXN1 VA AGND DGND V_REG Serial Audio Input 4:1 MUX Clock Generator Level Translators Receiver Clock & Data Recovery (PLL) 2:1 MUX Sample...