CY7C4281 Datasheet | Cypress

CY7C4281 CY7C4291 64K/128K x 9 Deep Sync FIFOs Features - High-speed, low-power, first-in first-out (FIFO) memories - 64K × 9 (CY7C4281) - 128K × 9 (CY7C4291) - 0.5-micron CMOS for optimum speed/power - High-speed 100-MHz operation (10-ns read/write cycle times) - Low power - ICC= 40 m A - ISB = 2 m A - Fully asynchronous and simultaneous read and write operation - Empty, Full, and programmable Almost Empty and Almost Full status flags - TTL patible - Output Enable (OE) pin - Independent read and write enable pins - Center power and ground pins for reduced noise - Supports free-running 50% duty cycle clock inputs - Width Expansion Capability - 32-pin PLCC - Pin-patible density upgrade to CY7C42X1 family - Pin-patible density upgrade to IDT72201/11/21/31/41/51 Logic Block Diagram D0 - 8 INPUT REGISTER Functional Description The CY7C4281/91 are high-speed, low-power FIFO memories with clocked read and write interfaces. All are nine...