CY14B256Q1 Datasheet | Cypress

Features - - 256-Kbit nonvolatile static random access memory (nv SRAM) - Internally organized as 32 K × 8 - STORE to Quantum Trap nonvolatile elements initiated automatically on power-down (Auto Store) or by user using HSB pin (Hardware STORE) or SPI instruction (Software STORE) - RECALL to SRAM initiated on power-up (Power-Up RECALL) or by SPI instruction (Software RECALL) - Automatic STORE on power-down with a small capacitor (except for CY14B256Q1) High reliability - Infinite read, write, and RECALL cycles - 1 million STORE cycles to Quantum Trap - Data retention: 20 years High-speed serial peripheral interface (SPI) - 40-MHz clock rate - Supports SPI mode 0 (0,0) and mode 3 (1,1) Write protection - Hardware protection using Write Protect (WP) pin - Software protection using Write Disable instruction - Software block protection for 1/4,1/2, or entire array Low power consumption - Single 3 V +20%, - 10% operation - Average active current of 10 m A at 40-MHz operation Industry standard configurations - Industrial temperature - CY14B256Q1 has identical pin configuration to industry standard 8-pin NV memory - 8-pin dual flat no-lead (DFN) package and 16-pin small outline integrated circuit (SOIC) package - Restriction of hazardous substances (Ro HS) pliant Functional Overview The Cypress CY14B256Q1/CY14B256Q2/CY14B256Q3 bines a 256-Kbit nv SRAM[1] with a nonvolatile element in each memory cell with serial SPI interface. The memory is organized as 32 K words of 8 bits each. The embedded nonvolatile elements incorporate the Quantum Trap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the Quantum Trap cell provides highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down (except for CY14B256Q1). On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). The STORE and...