Datasheet4U Logo Datasheet4U.com

CY24212 - MediaClock MPEG Clock Generator

Key Features

  • Benefits.
  • Integrated phase-locked loop (PLL).
  • Low jitter, high-accuracy outputs.
  • VCXO with analog adjust.
  • 3.3V operation.
  • Highest-performance PLL tailored for multimedia.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
CY24293 Two Outputs PCI-Express Clock Generator Cypress
CY2412 MPEG Clock Generator Cypress
CY24488 Quad-PLL Clock Generator Cypress
CY24APS Quartz Crystal Low Profile HC49S Leaded Crystal Crystek Corporation
CY24APSMD Quartz Crystal Surface Mount HC49S SMD Crystal Crystek Corporation

Other Datasheets by Cypress (now Infineon)

Part Number Description
CY24239 Spread Spectrum Frequency Timing Generator
CY24271 Clock Generator
CY24272 Rambus XDR Clock Generator
CY24292 Four Outputs PCI-Express Clock Generator
CY2410 MPEG Clock Generator

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
PRELIMINARY CY24212 MediaClock™ MPEG Clock Generator with VCXO Features Benefits ■ Integrated phase-locked loop (PLL) ■ Low jitter, high-accuracy outputs ■ VCXO with analog adjust ■ 3.3V operation ■ Highest-performance PLL tailored for multimedia applications ■ Meets critical timing requirements in complex system designs ■ Large ±150-ppm range, better linearity ■ Enables application compatibility Part Number CY24212-1 CY24212-2 CY24212-3 CY24212-5 Outputs 1 2 2 2 Input Frequency Range 13.5 MHz/27 MHz (selectable) 13.5 MHz/27 MHz (selectable) 27 MHz 27 MHz Output Frequencies 27 MHz Two copies of 27 MHz 27 MHz/27.027 MHz (-1 ppm) 27 MHz/27.027 MHz (0 ppm) Logic Block Diagram XIN XOUT VCXO OSC FSEL QΦ VCO P PLL VDD VSS OUTPUT DIVIDERS Table 1.