CY24212 Datasheet | Cypress

PRELIMINARY Media Clock™ MPEG Clock Generator with VCXO Features Benefits - Integrated phase-locked loop (PLL) - Low jitter, high-accuracy outputs - VCXO with analog adjust - 3.3V operation - Highest-performance PLL tailored for multimedia applications - Meets critical timing requirements in plex system designs - Large ±150-ppm range, better linearity - Enables application patibility Part Number CY24212-1 CY24212-2 CY24212-3 CY24212-5 Outputs 1 2 2 2 Input Frequency Range 13.5 MHz/27 MHz (selectable) 13.5 MHz/27 MHz (selectable) 27 MHz 27 MHz Output Frequencies 27 MHz Two copies of 27 MHz 27 MHz/27.027 MHz (-1 ppm) 27 MHz/27.027 MHz (0 ppm) Logic Block Diagram XIN XOUT VCXO FSEL QΦ P PLL VDD VSS OUTPUT DIVIDERS Table 1. CY24212 (-1, -2) Frequency Select Option FSEL 0 1 Reference 13.5 MHz 27 MHz CLKA/CLKB 27 MHz 27 MHz Table 2. CY24212 (-3, -5) Frequency Select...