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CY28RS480 - Clock Generator

Description

Pin No.

41,40,45,44 50 37 52, 53, 54 7 8 27, 28, 30, 29 12, 13, 16, 17, 18, 19, 22, 23, 24, 25, 34, 33 10,11 Name CPUT/C PCI0 IREF REF[2:0] SCLK SDATA SRCST/C[1:0] SRCT/C[5:0] Type O I 33-MHz clock output.

A precision resistor attached to this pin is connected to the internal current reference.

Features

  • Supports AMD CPU.
  • 200-MHz differential CPU clock pairs.
  • 100-MHz differential SRC clocks.
  • 48-MHz USB clock.
  • 33-MHz PCI clock.
  • 66-MHz HyperTransport clock.
  • I2C support with readback capabilities.
  • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction.
  • 3.3V power supply.
  • 56-pin SSOP and TSSOP packages CPU x2 SRC x8 HTT66 x1 PCI x1 REF x3 USB_48 x1 Block Diagram XIN X.

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Full PDF Text Transcription

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CY28RS480 Clock Generator for ATI RS480 Chipset Features • Supports AMD CPU • 200-MHz differential CPU clock pairs • 100-MHz differential SRC clocks • 48-MHz USB clock • 33-MHz PCI clock • 66-MHz HyperTransport clock • I2C support with readback capabilities • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • 3.3V power supply • 56-pin SSOP and TSSOP packages CPU x2 SRC x8 HTT66 x1 PCI x1 REF x3 USB_48 x1 Block Diagram XIN XOUT CPU_STP# CLKREQ[0:1]# Pin Configuration VDD_REF REF[0:2] VDD_CPU CPUT[0:1], CPUC[0:1], VDD_SRC SRCT[0:5],SRCC[0:5] VDD_SRCS SRCST[0:1],SRCSC[0:1] VDD_PCI PCI VDD_HTT HTT66 XTAL OSC PLL1 PLL Ref Freq Divider Network IREF www.DataSheet.co.
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