CY2SSTU877 Overview
The CY2SSTU877 is a high-performance, low-skew, low-jitter zero delay buffer designed to distribute differential clocks in high-speed applications. The CY2SSTU877 generates ten differential pair clock outputs from one differential pair clock input. In addition, the CY2SSTU877.
CY2SSTU877 Key Features
- Operating frequency: 125 MHz to 500 MHz
- Supports DDRII SDRAM
- Ten differential outputs from one differential input
- Spread-Spectrum-patible
- Low jitter (cycle-to-cycle): < 40 ps
- Very low skew: < 40 ps
- Power management control input
- 1.8V operation
- Fully JEDEC-pliant