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CY37128VP160-125AC - 5V/ 3.3V/ ISR High-Performance CPLDs

This page provides the datasheet information for the CY37128VP160-125AC, a member of the CY3 5V/ 3.3V/ ISR High-Performance CPLDs family.

Datasheet Summary

Description

The Ultra37000™ family of CMOS CPLDs provides a range of high-density programmable logic solutions with unparalleled system performance.

The Ultra37000 family is designed to bring the flexibility, ease of use, and performance of the 22V10 to high-density CPLDs.

Features

  • In-System Reprogrammable™ (ISR™) CMOS CPLDs.
  • JTAG interface for reconfigurability.
  • Design changes do not cause pinout changes.
  • Design changes do not cause timing changes.
  • High density.
  • 32 to 512 macrocells.
  • 32 to 264 I/O pins.
  • Five dedicated inputs including four clock pins.
  • Simple timing model.
  • No fanout delays.
  • No expander delays.
  • No dedicated vs. I/O pin delays.
  • No additional.

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Datasheet preview – CY37128VP160-125AC

Datasheet Details

Part number CY37128VP160-125AC
Manufacturer Cypress Semiconductor
File Size 1.55 MB
Description 5V/ 3.3V/ ISR High-Performance CPLDs
Datasheet download datasheet CY37128VP160-125AC Datasheet
Additional preview pages of the CY37128VP160-125AC datasheet.

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Full PDF Text Transcription

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Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs Features • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated inputs including four clock pins • Simple timing model — No fanout delays — No expander delays — No dedicated vs. I/O pin delays — No additional delay through PIM — No penalty for using full 16 product terms • • • • — No delay for steering or sharing product terms 3.
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