CY62146EV30 Datasheet | Cypress

CY62146EV30 Mo BL® 4-Mbit (256K x 16) Static RAM Features - Very high speed: 45 ns - Wide voltage range: 2.20V- 3.60V - Pin patible with CY62146DV30 - Ultra low standby power - Typical standby current: 1 µA - Maximum standby current: 7 µA - Ultra low active power - Typical active current: 2 m A @ f = 1 MHz - Easy memory expansion with CE, and OE Features - Automatic power down when deselected - CMOS for optimum speed and power - Available in a Pb-free 48-ball VFBGA and 44-pin TSOP II packages reduces power consumption by 80% when addresses are not toggling. The device can also be put into standby mode reducing power consumption by more than 99% when deselected (CE HIGH). The input and output pins (IO0 through IO15) are placed in a high impedance state when: - Deselected (CE HIGH) - Outputs are disabled (OE HIGH) - Both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) - Write operation is active (CE LOW and WE LOW) Write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A17). Read from the device by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See the “Truth Table” on page 9 for a plete description of read and write modes. Functional Description [1] The CY62146EV30 is a high performance CMOS static RAM organized as 256K words by 16 bits. This device Features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (Mo BL®) in...