CY62168DV30 Datasheet | Cypress

.. CY62168DV30 Mo BL 16-Mbit (2048K x 8) Static RAM Features - Very high speed: 55 ns and 70 ns - Wide voltage range: 2.20V - 3.60V - Ultra-low active power - Typical active current: 2 m A @ f = 1 MHz - Typical active current: 15 m A @ f = fmax - Ultra-low standby power - Easy memory expansion with CE1, CE2 and OE Features - Automatic power-down when deselected - CMOS for optimum speed/power - Packages offered in a 48-ball FBGA addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW. The input/output pins (I/O0 through I/O7) are placed in a high-impedance state when: deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW, outputs are disabled (OE HIGH), or during a write operation (Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and WE LOW). Writing to the device is acplished by taking Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable (WE) input LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins(A0 through A20). Reading from the device is acplished by taking Chip Enable 1 (CE1) and Output Enable (OE) LOW and Chip Enable 2 (CE2) HIGH while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. Functional Description[1] The CY62168DV30 is a high-performance CMOS static RAMs The eight input/output pins (I/O0 through I/O7) are placed in a organized as 2048Kbit words by 8 bits. This device Features high-impedance state when the device is deselected (CE1 advanced circuit design to provide ultra-low active current. LOW and CE2 HIGH), the outputs are disabled (OE HIGH), or This is ideal for providing More Battery Life (Mo BL) in during a write operation (CE1 LOW and CE2 HIGH and WE portable applications such as cellular telephones....