CY62168EV30 Datasheet | Cypress

CY62168EV30 Mo BL® 16-Mbit (2 M × 8) Static RAM 16-Mbit (2 M × 8) Static RAM Features - - - Very high speed: 45 ns Wide voltage range: 2.20 V to 3.60 V Ultra low standby power - Typical standby current: 1.5 µA - Maximum standby current: 12 µA Ultra low active power - Typical active current: 2.2 m A at f = 1 MHz Easy memory expansion with CE1, CE2 and OE Features Automatic power-down when deselected CMOS for optimum speed/power Offered in Pb-free 48-ball FBGA package. For Pb-free 48-pin TSOP I package, refer to CY62167EV30 datasheet. - automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW). The input and output pins (I/O0 through I/O7) are placed in a high impedance state when: the device is deselected (Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW), outputs are disabled (OE HIGH), or a write operation is in progress (Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and WE LOW). Write to the device by taking Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and the Write Enable (WE) input LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A20). Read from the device by taking Chip Enable 1 (CE1) and Output Enable (OE) LOW and Chip Enable 2 (CE2) HIGH while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a write operation is in progress (CE1 LOW and CE2 HIGH and WE LOW). See the Truth Table on page 11 for a plete description of read and write modes. - - - - Functional Description The...