CY7B9911
Overview
- All output pair skew <100 ps typical (250 max.)
- 3.75- to 110-MHz output operation
- User-selectable output functions - Selectable skew to 18 ns - Inverted and non-inverted - Operation at 1⁄2 and 1⁄4 input frequency - Operation at 2x and 4x input frequency (input as low as 3.75 MHz) Zero input-to-output delay 50% duty-cycle outputs LVTTL outputs drive 50Ω terminated lines Operates from a single 3.3V supply Low operating current 32-pin PLCC package Jitter < 200 ps peak-to-peak (< 25 ps RMS) selectable control over system clock functions. These multipleoutput clock drivers provide the system integrator with functions necessary to optimize the timing of high-performance computer systems. Eight individual drivers, arranged as four pairs of user-controllable outputs, can each drive terminated transmission lines with impedances as low as 50Ω while delivering minimal and specified output skews and full-swing logic levels (LVTTL). Each output can be hardwired to one of nine delay or function configurations. Delay increments of 0.7 to 1.5 ns are determined by the operating frequency with outputs able to skew up to ±6 time units from their nominal “zero” skew position. The completely integrated PLL allows external load and transmission line delay effects to be canceled. When this “zero delay” capability of the LVPSCB is combined with the selectable output skew functions, the user can create output-to-output delays of up to ±12 time units. Divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. When combined with the internal PLL, these divide functions allow distribution of a low-frequency clock that can be multiplied by two or four at the clock destination. This facility minimizes clock distribution difficulty while allowing maximum system clock speed and flexibility. *
