CY7C027
Features
True dual-ported memory cells which allow simultaneous access of the same memory location
- 32 K × 16 organization (CY7C027)
- 64 K × 16 organization (CY7C028)
- 0.35 micron CMOS for optimum speed and power
- High speed access: 15 and 20 ns
- Low operating power
- Active: ICC = 180 m A (typical)
- Standby: ISB3 = 0.05 m A (typical)
- Fully asynchronous operation
- Automatic power down
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- Expandable data bus to 32 bits or more using Master/Slave chip select when using more than one device On-chip arbitration logic Semaphores included to permit software handshaking between ports INT flags for port-to-port munication Separate upper-byte and lower-byte control Dual chip enables Pin select for Master or Slave mercial and industrial temperature ranges Available in 100-pin TQFP Pb-free packages available
R/WR UBR
Logic Block Diagram
R/WL UBL
CE0L CE1L LBL OEL
CE0R CE1R LBR OER
I/O8L- I/O15L I/O0L- I/O7L
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8 8
I/O Control
I/O...
