CY7C0830V Overview
Key Features
- True dual-ported memory cells that allow simultaneous access of the same memory location
- Synchronous pipelined operation
- Pipelined output mode allows fast operation
- 0.18-micron CMOS for optimum speed and power
- High-speed clock to data access
- 3.3V low power
- Active as low as 225 mA (typ)
- Internal mask register controls counter wrap-around
- Counter-interrupt flags to indicate wrap-around
- Memory block retransmit operation
