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CY7C1046DV33 - 4-Mbit (1 M x 4) Static RAM

General Description

The CY7C1046DV33 is a high-performance CMOS static RAM organized as 1M words by 4 bits.

Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers.

Key Features

  • Pin- and function-compatible with CY7C1046CV33.
  • High speed.
  • tAA = 10 ns.
  • Low active power.
  • ICC = 90 mA @ 100 MHz.
  • Low CMOS standby power.
  • ISB2 = 10 mA.
  • 2.0 V data retention.
  • Automatic power-down when deselected.
  • TTL-compatible inputs and outputs.
  • Easy memory expansion with CE and OE features.
  • Available in lead-free 400-mil-wide 32-pin SOJ package Logic Block Diagram Functional.

📥 Download Datasheet

Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C1046D 4-Mbit (1 M x 4) Static RAM
CY7C1041 256K x 16 Static RAM
CY7C1041B 256K x 16 Static RAM
CY7C1041BN 256K x 16 Static RAM
CY7C1041BV33 256K x 16 Static RAM
CY7C1041CV33 256K x 16 Static RAM
CY7C1041D 4-Mbit (256K x 16) Static RAM
CY7C1041DV33 4-Mbit (256K x 16) Static RAM
CY7C1041V33 256K x 16 Static RAM
CY7C1049 512K x 8 Static RAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CY7C1046DV33 4-Mbit (1 M × 4) Static RAM 4-Mbit (1 M × 4) Static RAM Features ■ Pin- and function-compatible with CY7C1046CV33 ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 90 mA @ 100 MHz ■ Low CMOS standby power ❐ ISB2 = 10 mA ■ 2.0 V data retention ■ Automatic power-down when deselected ■ TTL-compatible inputs and outputs ■ Easy memory expansion with CE and OE features ■ Available in lead-free 400-mil-wide 32-pin SOJ package Logic Block Diagram Functional Description The CY7C1046DV33 is a high-performance CMOS static RAM organized as 1M words by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW.