CY7C1049D Datasheet | Cypress

4-Mbit (512K x 8) Static RAM Features - Pin- and function-patible with CY7C1049B - High speed - t AA = 10 ns - Low active power - ICC = 90 m A @ 10 ns .. Functional Description[1] The CY7C1049D is a high-performance CMOS static RAM organized as 512K words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. Writing to the device is acplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is acplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1049D is available in a standard 400-mil-wide 36-pin SOJ package with center power and ground (revolutionary) pinout. - Low CMOS Standby power - ISB2 = 10 m A - 2.0V Data Retention - Automatic power-down when deselected - TTL-patible inputs and outputs - Easy memory expansion with CE and OE Features - Available in lead-free 36-Lead (400-Mil) Molded SOJ package Logic Block Diagram Pin Configuration SOJ Top View A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 A16 A15 OE I/O7 I/O6 GND VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC I/O0 INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 I/O1 ROW DECODER I/O2 SENSE AMPS 512K x 8 I/O3 I/O4...