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CY7C1148V18 - (CY7C11xxV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture

This page provides the datasheet information for the CY7C1148V18, a member of the CY7C1146V18 (CY7C11xxV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture family.

Datasheet Summary

Description

The CY7C1146V18, CY7C1157V18, CY7C1148V18, and CY7C1150V18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II+ architecture.

The DDR-II+ consists of an SRAM core with advanced synchronous peripheral circuitry.

Features

  • Functional.

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Datasheet preview – CY7C1148V18

Datasheet Details

Part number CY7C1148V18
Manufacturer Cypress Semiconductor
File Size 1.15 MB
Description (CY7C11xxV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture
Datasheet download datasheet CY7C1148V18 Datasheet
Additional preview pages of the CY7C1148V18 datasheet.

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Full PDF Text Transcription

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CY7C1146V18 CY7C1157V18 CY7C1148V18 CY7C1150V18 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features ■ ■ ■ ■ ■ ■ Functional Description The CY7C1146V18, CY7C1157V18, CY7C1148V18, and CY7C1150V18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II+ architecture. The DDR-II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 8-bit words (CY7C1146V18) or 9-bit words (CY7C1157V18) or 18-bit words (CY7C1148V18) or 36-bit words (CY7C1150V18) that burst sequentially into or out of the device.
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