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CY7C1176KV18 - 18-Mbit QDR II SRAM Four-Word Burst Architecture

This page provides the datasheet information for the CY7C1176KV18, a member of the CY7C1161KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture family.

Description

The CY7C1161KV18, CY7C1176KV18, CY7C1163KV18, and CY7C1165KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture.

Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array.

Features

  • Configurations With Read Cycle Latency of 2.5 cycles: CY7C1161KV18.
  • 2 M x 8 CY7C1176KV18.
  • 2 M x 9 CY7C1163KV18.
  • 1 M x 18 CY7C1165KV18.
  • 512 K x 36 Separate independent read and write data ports.
  • Supports concurrent transactions 550-MHz clock for high bandwidth Four-word burst for reducing address bus frequency Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz Available in 2.5 clock cycle latenc.

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Datasheet preview – CY7C1176KV18

Datasheet Details

Part number CY7C1176KV18
Manufacturer Cypress Semiconductor
File Size 908.73 KB
Description 18-Mbit QDR II SRAM Four-Word Burst Architecture
Datasheet download datasheet CY7C1176KV18 Datasheet
Additional preview pages of the CY7C1176KV18 datasheet.

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Full PDF Text Transcription

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CY7C1161KV18, CY7C1176KV18 CY7C1163KV18, CY7C1165KV18 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features ■ Configurations With Read Cycle Latency of 2.5 cycles: CY7C1161KV18 – 2 M x 8 CY7C1176KV18 – 2 M x 9 CY7C1163KV18 – 1 M x 18 CY7C1165KV18 – 512 K x 36 Separate independent read and write data ports ❐ Supports concurrent transactions 550-MHz clock for high bandwidth Four-word burst for reducing address bus frequency Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz Available in 2.
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