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CY7C1219F - 1-Mbit (32K x 36) Pipelined DCD Sync SRAM

Datasheet Summary

Description

The CY7C1219F SRAM integrates 32,768 x 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation.

All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).

Features

  • Registered inputs and outputs for pipelined operation.
  • Optimal for performance (Double-Cycle deselect).
  • Depth expansion without wait state.
  • 32K × 36-bit common I/O architecture.
  • 3.3V.
  • 5% and +10% core power supply (VDD).
  • 3.3V I/O supply (VDDQ).
  • Fast clock-to-output times.
  • 3.5 ns (for 166-MHz device).
  • 4.0 ns (for 133-MHz device).
  • Provide high-performance 3-1-1-1 access rate.
  • User-selectable.

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Datasheet preview – CY7C1219F

Datasheet Details

Part number CY7C1219F
Manufacturer Cypress Semiconductor
File Size 375.20 KB
Description 1-Mbit (32K x 36) Pipelined DCD Sync SRAM
Datasheet download datasheet CY7C1219F Datasheet
Additional preview pages of the CY7C1219F datasheet.

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CY7C1219F www.DataSheet4U.com 1-Mbit (32K x 36) Pipelined DCD Sync SRAM Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 32K × 36-bit common I/O architecture • 3.3V –5% and +10% core power supply (VDD) • 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 3.5 ns (for 166-MHz device) — 4.
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