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CY7C1231F - 2Mbit Flow-Through SRAM

Description

The CY7C1231F is a 3.3V, 128K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.

Features

  • Can support up to 117-MHz bus operations with zero wait states.
  • Data is transferred on every clock w w.
  • Pin compatible and functionally equivalent to ZBT™ devices.
  • Internally self-timed output buffer control to eliminate the need to use OE.
  • Registered inputs for flow-through operation.
  • Byte Write capability.
  • 128K x 18 common I/O architecture.
  • Single 3.3V power supply.
  • Fast clock-to-output times.
  • 7.5 ns.

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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1212F 1-Mbit (64K x 18) Pipelined Sync SRAM
CY7C1212H 1-Mbit (64K x 18) Pipelined Sync SRAM
CY7C1214F 1-Mb (32K x 32) Flow-Through Sync SRAM
CY7C1214H 1-Mbit (32K x 32) Flow-Through Sync SRAM
CY7C1215F 1-Mb (32K x 32) Pipelined Sync SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Features • Can support up to 117-MHz bus operations with zero wait states — Data is transferred on every clock w w • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through operation • Byte Write capability • 128K x 18 common I/O architecture • Single 3.3V power supply • Fast clock-to-output times — 7.5 ns (for 117-MHz device) — 8.5 ns (for 100-MHz device) • Clock Enable (CEN) pin to suspend operation • Synchronous self-timed writes • Asynchronous Output Enable • JEDEC-standard 100 TQFP package • Low standby power • Burst Capability—linear or interleaved burst order w .D at h S a ee U 4 t .
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