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CY7C1311BV18 Datasheet (cy7c1x1xbv18) 18-mb Qdrtm-ii Sram 4-word Burst Architecture

Manufacturer: Cypress (now Infineon)

Overview: CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR™-II SRAM 4-Word Burst.

General Description

The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture.

QDR-II architecture consists of two separate ports to access the memory array.

The Read port has dedicated Data Outputs to support Read operations and the Write port has dedicated Data Inputs to support Write operations.

Key Features

  • Separate Independent Read and Write data ports.
  • Supports concurrent transactions.
  • 300-MHz clock for high bandwidth.
  • 4-Word Burst for reducing address bus frequency.
  • Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 600 MHz) at 300 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two input clocks for output data (C and C) to minimize clock-skew and flight-.

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