Datasheet4U Logo Datasheet4U.com

CY7C1318AV18 - 18-Mbit DDR-II SRAM 2-Word Burst Architecture

This page provides the datasheet information for the CY7C1318AV18, a member of the CY7C1316AV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture family.

Datasheet Summary

Description

The CY7C1316AV18/CY7C1318AV18/CY7C1320AV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture.

The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter.

Features

  • 18-Mb density (2M x 8, 1M x 18, 512K x 36).
  • 250-MHz clock for high bandwidth.
  • 2-Word burst for reducing address bus frequency.
  • Double Data Rate (DDR) interfaces (data transferred at 500 MHz) @ 250 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two output clocks (C and C) account for clock skew and flight time mismatching.
  • Echo clocks (CQ and CQ) simplify data capture in high-speed syste.

📥 Download Datasheet

Datasheet preview – CY7C1318AV18

Datasheet Details

Part number CY7C1318AV18
Manufacturer Cypress Semiconductor
File Size 267.53 KB
Description 18-Mbit DDR-II SRAM 2-Word Burst Architecture
Datasheet download datasheet CY7C1318AV18 Datasheet
Additional preview pages of the CY7C1318AV18 datasheet.

📁 Similar Datasheet

  • CY7C131AE - 1K/2K x 8 Dual-Port Static RAM (Cypress)
  • CY7C131E - 1K/2K x 8 Dual-Port Static RAM (Cypress)
  • CY7C136AE - 1K/2K x 8 Dual-Port Static RAM (Cypress)
  • CY7C136E - 1K/2K x 8 Dual-Port Static RAM (Cypress)
  • CY7C1370C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
  • CY7C1370CV25 - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
  • CY7C1370D - 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM (Cypress)
  • CY7C1371C - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture (Cypress)
  • CY7C1371S - 18-Mbit (512K x 36) Flow-Through SRAM (Cypress)
  • CY7C1372C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
Other Datasheets by Cypress Semiconductor
  • CY7C1318BV18 - 18-Mbit DDR-II SRAM 2-Word Burst Architecture
  • CY7C1318CV18 - (CY7C1xxxCV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture
  • CY7C1318JV18 - 18-Mbit DDR-II SRAM 2-Word Burst Architecture
  • CY7C1318KV18 - 18-Mbit DDR II SRAM Two-Word Burst Architecture
  • CY7C131 - 1K x 8 Dual-Port Static RAM
  • CY7C1310BV18 - 1.8V Synchronous Pipelined SRAM
  • CY7C1311AV18 - (CY7C131xAV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
  • CY7C1311BV18 - (CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture

Full PDF Text Transcription

Click to expand full text
CY7C1316AV18 CY7C1318AV18 CY7C1320AV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features • 18-Mb density (2M x 8, 1M x 18, 512K x 36) • 250-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at 500 MHz) @ 250 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two output clocks (C and C) account for clock skew and flight time mismatching • Echo clocks (CQ and CQ) simplify data capture in high-speed systems • Synchronous internally self-timed writes • 1.8V core power supply with HSTL inputs and outputs • Variable drive HSTL output buffers • Expanded HSTL output voltage (1.4V–VDD) • 13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball (11x15 matrix) • JTAG 1149.
Published: |