CY7C1318AV18
Key Features
- 250-MHz clock for high bandwidth
- 2-Word burst for reducing address bus frequency
- Double Data Rate (DDR) interfaces (data transferred at 500 MHz) @ 250 MHz
- Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only
- Two output clocks (C and C) account for clock skew and flight time mismatching
- Echo clocks (CQ and CQ) simplify data capture in high-speed systems
- Synchronous internally self-timed writes
- 1.8V core power supply with HSTL inputs and outputs
- Variable drive HSTL output buffers
- Expanded HSTL output voltage (1.4V–VDD)
