CY7C1318KV18 Overview
The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K.
CY7C1318KV18 Key Features
- 2 M × 8 CY7C1916KV18
- 2 M × 9 CY7C1318KV18
- 1 M × 18 CY7C1320KV18
- 512 K × 36
- SRAM uses rising edges only Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
- Supports both 1.5 V and 1.8 V I/O supply Available in 165-ball FBGA package (13 × 15 × 1.4 mm) Offered in both Pb-free a