CY7C1323BV25 Description
18-Mbit Density (512 Kbit x 36) 167-MHz Clock for high bandwidth 4-Word Burst for reducing address bus frequency Double Data Rate (DDR) interfaces (data transferred at 333 MHz @ 167 MHz) Two input clocks (K and K) for precise DDR timing SRAM uses rising edges only Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches. The DDR-I architecture consists.
CY7C1323BV25 Key Features
- 18-Mbit Density (512 Kbit x 36)
- 167-MHz Clock for high bandwidth
- 4-Word Burst for reducing address bus frequency
- Double Data Rate (DDR) interfaces (data transferred at
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Two input clocks for output data (C and C) to minimize
- Separate Port Selects for depth expansion
- Synchronous internally self-timed writes
- 2.5V core power supply with HSTL Inputs and Outputs