CY7C1323BV25
Features
Functional Description
- 18-Mbit Density (512 Kbit x 36)
- 167-MHz Clock for high bandwidth
- 4-Word Burst for reducing address bus frequency
- Double Data Rate (DDR) interfaces (data transferred at
333 MHz @ 167 MHz)
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches.
- Separate Port Selects for depth expansion
- Synchronous internally self-timed writes
- 2.5V core power supply with HSTL Inputs and Outputs
- Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
- Variable drive HSTL output buffers
- Expanded HSTL output voltage (1.4V- 1.9V)
- JTAG 1149.1 patible test access port
Configuration
- 256K x 36
The CY7C1323BV25 is a 2.5V Synchronous Pipelined SRAM equipped with DDR-I (Double Data Rate) architecture. The DDR-I architecture...
