Datasheet Details
| Part number | CY7C1323BV25 |
|---|---|
| Manufacturer | Cypress (now Infineon) |
| File Size | 659.00 KB |
| Description | 18-Mbit 4-Word Burst SRAM |
| Download | CY7C1323BV25 Download (PDF) |
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| Part number | CY7C1323BV25 |
|---|---|
| Manufacturer | Cypress (now Infineon) |
| File Size | 659.00 KB |
| Description | 18-Mbit 4-Word Burst SRAM |
| Download | CY7C1323BV25 Download (PDF) |
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• 18-Mbit Density (512 Kbit x 36) • 167-MHz Clock for high bandwidth • 4-Word Burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at 333 MHz @ 167 MHz) • Two input clocks (K and K) for precise DDR timing – SRAM uses rising edges only • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches.
• Separate Port Selects for depth expansion • Synchronous internally self-timed writes • 2.5V core power supply with HSTL Inputs and Outputs • Available in 165-ball FBGA package (13 x 15 x 1.4 mm) • Variable drive HSTL output buffers • Expanded HSTL output voltage (1.4V–1.9V) • JTAG 1149.1 compatible test access port Configuration CY7C1323BV25 - 256K x 36 The CY7C1323BV25 is a 2.5V Synchronous Pipelined SRAM equipped with DDR-I (Double Data Rate) architecture.
The DDR-I architecture consists
CY7C1323BV25 18-Mbit 4-Word Burst SRAM with DDR-I Architecture.
| Part Number | Description |
|---|---|
| CY7C132 | 2K x 8 Dual-Port Static RAM |
| CY7C1320AV18 | 18-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1320BV18 | 18-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1320CV18 | (CY7C1xxxCV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1320JV18 | 18-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1320KV18 | 18-Mbit DDR II SRAM Two-Word Burst Architecture |
| CY7C1321BV18 | 1.8V Synchronous Pipelined SRAM |
| CY7C1321KV18 | 18-Mbit DDR II SRAM Four-Word Burst Architecture |
| CY7C1325 | 256K x 18 Synchronous 3.3V Cache RAM |
| CY7C1325G | 4-Mbit (256K 횞 18) Flow-Through Sync SRAM |