Datasheet4U Logo Datasheet4U.com

CY7C1323BV25 - 18-Mbit 4-Word Burst SRAM

Description

18-Mbit Density (512 Kbit x 36) 167-MHz Clock for high bandwidth 4-Word Burst for reducing address bus frequency Double Data Rate (DDR) interfaces (data transferred at 333 MHz @ 167 MHz) Two input clocks (K and K) for precise DDR timing SR

Features

  • Functional.

📥 Download Datasheet

Datasheet preview – CY7C1323BV25

📁 Similar Datasheet

  • CY7C131AE - 1K/2K x 8 Dual-Port Static RAM (Cypress)
  • CY7C131E - 1K/2K x 8 Dual-Port Static RAM (Cypress)
  • CY7C136AE - 1K/2K x 8 Dual-Port Static RAM (Cypress)
  • CY7C136E - 1K/2K x 8 Dual-Port Static RAM (Cypress)
  • CY7C1370C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
  • CY7C1370CV25 - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
  • CY7C1370D - 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM (Cypress)
  • CY7C1371C - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture (Cypress)
  • CY7C1371S - 18-Mbit (512K x 36) Flow-Through SRAM (Cypress)
  • CY7C1372C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
Other Datasheets by Cypress Semiconductor
  • CY7C132 - 2K x 8 Dual-Port Static RAM
  • CY7C1320AV18 - 18-Mbit DDR-II SRAM 2-Word Burst Architecture
  • CY7C1320BV18 - 18-Mbit DDR-II SRAM 2-Word Burst Architecture
  • CY7C1320CV18 - (CY7C1xxxCV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture
  • CY7C1320JV18 - 18-Mbit DDR-II SRAM 2-Word Burst Architecture
  • CY7C1320KV18 - 18-Mbit DDR II SRAM Two-Word Burst Architecture
  • CY7C1321BV18 - 1.8V Synchronous Pipelined SRAM
  • CY7C1321KV18 - 18-Mbit DDR II SRAM Four-Word Burst Architecture

Full PDF Text Transcription

Click to expand full text
CY7C1323BV25 18-Mbit 4-Word Burst SRAM with DDR-I Architecture Features Functional Description • 18-Mbit Density (512 Kbit x 36) • 167-MHz Clock for high bandwidth • 4-Word Burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at 333 MHz @ 167 MHz) • Two input clocks (K and K) for precise DDR timing – SRAM uses rising edges only • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches. • Separate Port Selects for depth expansion • Synchronous internally self-timed writes • 2.5V core power supply with HSTL Inputs and Outputs • Available in 165-ball FBGA package (13 x 15 x 1.4 mm) • Variable drive HSTL output buffers • Expanded HSTL output voltage (1.4V–1.9V) • JTAG 1149.
Published: |