CY7C1354CV25 Overview
CY7C1354CV25 CY7C1356CV25 9-Mbit (256K × 36/512K × 18) Pipelined SRAM with NoBL™ Architecture 9-Mbit (256K × 36/512K × 18) Pipelined SRAM with NoBL™.
CY7C1354CV25 Key Features
- Pin-patible with and functionally equivalent to ZBT™
- Supports 250-MHz bus operations with zero wait states
- Available speed grades are 250, 200, and 166 MHz
- Internally self-timed output buffer control to eliminate the need
- Fully registered (inputs and outputs) for pipelined operation
- Byte write capability
- Single 2.5 V power supply (VDD)
- Fast clock-to-output times
- 2.8 ns (for 250-MHz device)
- Clock enable (CEN) pin to suspend operation