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CY7C1361C Datasheet (cy7c1361c / Cy7c1363c) 9-mbit (256k X 36/512k X 18) Flow-through Sram

Manufacturer: Cypress (now Infineon)

Overview: PRELIMINARY CY7C1361C CY7C1363C 9-Mbit (256K x 36/512K x 18) Flow-Through.

This datasheet includes multiple variants, all published together in a single manufacturer document.

General Description

[1] The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flowthrough SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic.

Maximum access delay from clock rise is 6.5 ns (133-MHz version).

A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.

Key Features

  • Supports 133-MHz bus operations.
  • 256K × 36/512K × 18 common I/O.
  • 3.3V.
  • 5% and +10% core power supply (VDD).
  • 2.5V or 3.3V I/O supply (VDDQ).
  • Fast clock-to-output times.
  • 6.5 ns (133-MHz version).
  • 7.5 ns (117-MHz version).
  • 8.5 ns (100-MHz version).
  • Provide high-performance 2-1-1-1 access rate.
  • User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences.
  • Sepa.

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