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CY7C1361C - (CY7C1361C / CY7C1363C) 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM

Download the CY7C1361C datasheet PDF. This datasheet also covers the CY7C1363C variant, as both devices belong to the same (cy7c1361c / cy7c1363c) 9-mbit (256k x 36/512k x 18) flow-through sram family and are provided as variant models within a single manufacturer datasheet.

General Description

The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flowthrough SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic.

Maximum access delay from clock rise is 6.5 ns (133-MHz version).

Key Features

  • Supports 133-MHz bus operations.
  • 256K × 36/512K × 18 common I/O.
  • 3.3V.
  • 5% and +10% core power supply (VDD).
  • 2.5V or 3.3V I/O supply (VDDQ).
  • Fast clock-to-output times.
  • 6.5 ns (133-MHz version).
  • 7.5 ns (117-MHz version).
  • 8.5 ns (100-MHz version).
  • Provide high-performance 2-1-1-1 access rate.
  • User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences.
  • Sepa.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1363C_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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CY7C131E 1K/2K x 8 Dual-Port Static RAM Cypress
CY7C1370C 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Cypress

Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C136 2K x 8 Dual-Port Static RAM
CY7C1360C 9-Mbit Pipelined SRAM
CY7C1360V25 256K x 36/256K x 32/512K x 18 Pipelined SRAM
CY7C1362C 9-Mbit Pipelined SRAM
CY7C1362V25 256K x 36/256K x 32/512K x 18 Pipelined SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
PRELIMINARY CY7C1361C CY7C1363C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Features • Supports 133-MHz bus operations • 256K × 36/512K × 18 common I/O • 3.3V –5% and +10% core power supply (VDD) • 2.5V or 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version) — 7.5 ns (117-MHz version) — 8.5 ns (100-MHz version) • Provide high-performance 2-1-1-1 access rate • User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed write • Asynchronous output enable • Available in Lead-Free 100 TQFP,119 BGA and 165 fBGA packages Both 2 and 3 Chip Enable Options for TQFP • IEEE 1149.