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CY7C1371KV33 - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Key Features

  • No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles.
  • Supports up to 133-MHz bus operations with zero wait states.
  • Data is transferred on every clock.
  • Pin-compatible and functionally equivalent to ZBT™ devices.
  • Internally self-timed output buffer control to eliminate the need to use OE.
  • Registered inputs for flow through operation.
  • Byte write capability.
  • 3.3 V/2.5 V I/O power supply (VDDQ).
  • Fast clock-to-output ti.

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CY7C1370D 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM Cypress

Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C1371KVE33 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1371B (CY7C1371B / CY7C1373B) 512K x 36/1M x 18 Flow-Thru SRAM
CY7C1371D 18-Mbit (512 K x 36/1 M x 18) Flow-Through SRAM
CY7C1371DV25 (CY7C1371DV25 / CY7C1373DV25) Flow-Through SRAM
CY7C1370B (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CY7C1371KV33 CY7C1371KVE33 CY7C1373KV33 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM with NoBL™ Architecture (With ECC) 18-Mbit (512K × 36/1M × 18) Flow-through SRAM with NoBL™ Architecture (With ECC) Features ■ No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles ■ Supports up to 133-MHz bus operations with zero wait states ❐ Data is transferred on every clock ■ Pin-compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need to use OE ■ Registered inputs for flow through operation ■ Byte write capability ■ 3.3 V/2.5 V I/O power supply (VDDQ) ■ Fast clock-to-output times ❐ 6.