CY7C1371KV33 Description
CY7C1371KV33 CY7C1371KVE33 CY7C1373KV33 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM with NoBL™ Architecture (With ECC) 18-Mbit (512K × 36/1M × 18) Flow-through SRAM with NoBL™ Architecture (With.
CY7C1371KV33 Key Features
- No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles
- Supports up to 133-MHz bus operations with zero wait states
- Data is transferred on every clock
- Pin-patible and functionally equivalent to ZBT™ devices
- Internally self-timed output buffer control to eliminate the need
- Registered inputs for flow through operation
- Byte write capability
- 3.3 V/2.5 V I/O power supply (VDDQ)
- Fast clock-to-output times
- 6.5 ns (for 133-MHz device)