CY7C1386B Datasheet | Cypress

.. 86B CY7C1386B CY7C1387B 512K x 36/1M x 18 Pipelined DCD SRAM Features - - - - - - - - - - - - - Fast clock speed: 200, 167, 150, 133 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 3.0, 3.4, 3.8, and 4.2 ns Optimal for depth expansion 3.3V (- 5% / +10%) power supply mon data inputs and data outputs Byte Write Enable and Global Write control Double-cycle deselect Chip enable for address pipeline Address, data, and control registers Internally self-timed Write cycle Burst control pins (interleaved or linear burst sequence) Automatic power-down available using ZZ mode or CE deselect High-density, high-speed packages JTAG boundary scan for BGA packaging version Automatic power down available using ZZ mode or CE deselect registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, data inputs, address-pipelining Chip Enables (CEs), burst control inputs (ADSC, ADSP, and ADV), Write Enables (BWa, BWb, BWc, BWd and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and burst mode control (MODE). DQa,b,c,d and DPa,b,c,d apply to CY7C1386B and DQa,b and DPa,b apply to CY7C1387B. a, b, c, and d each are 8 bits wide in the case of DQ and 1 bit wide in the case of DP. Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance Pin (ADV). The CY7C1386B and CY7C1387B SRAMs integrate 524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by deselect parts. All inputs and outputs of the CY7C1386B and the CY7C1387B are JEDEC-standard JESD8-5-patible. Selection Guide 200 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 3 315 20 167 MHz 3.4...