CY7C1386C Datasheet | Cypress

.. CY7C1386C CY7C1387C 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM Features - Supports bus operation up to 250 MHz - Available speed grades are 250, 225, 200 and 167 MHz - Registered inputs and outputs for pipelined operation - Optimal for performance (Double-Cycle deselect) - Depth expansion without wait state - 3.3V - 5% and +10% core power supply (VDD) - 2.5V / 3.3V I/O operation - Fast clock-to-output times - 2.6 ns (for 250-MHz device) - 2.8 ns (for 225-MHz device) - 3.0 ns (for 200-MHz device) - 3.4 ns (for 167-MHz device) - Provide high-performance 3-1-1-1 access rate - - - - - Intel Functional Description[1] The CY7C1386C/CY7C1387C SRAM integrates 524,288 x 36 and 1048,576 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3[2]), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). - IEEE 1149.1 JTAG-patible Boundary Scan - “ZZ” Sleep Mode Option The CY7C1386C/CY7C1387C operates from a +3.3V core power supply while all outputs operate with a +3.3V or a +2.5V supply. All inputs and outputs are JEDEC-standard JESD8-5-patible. Selection Guide 250 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 2.6 350 70 225 MHz 2.8 325 70 200 MHz 3.0 300 70 167 MHz 3.4 275 70 Unit ns m A m A Shaded areas contain advance information. Please contact...