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CY7C1386D - 18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM

General Description

The CY7C1386D/CY7C1387D SRAM integrates 512K × 36/1M × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation.

All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK).

Key Features

  • Supports bus operation up to 200 MHz.
  • Available speed grades are 200, and 167 MHz.
  • Registered inputs and outputs for pipelined operation.
  • Optimal for performance (double-cycle deselect).
  • Depth expansion without wait state.
  • 3.3 V core power supply (VDD).
  • 2.5 V or 3.3 V I/O power supply (VDDQ).
  • Fast clock-to-output times.
  • 3 ns (for 200 MHz device).
  • Provides high performance 3-1-1-1 access rate.
  • User selectable burst counter supporting Intel.

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Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C1386B (CY7C1386B / CY7C1387B) 512K x 36/1M x 18 Pipelined DCD SRAM
CY7C1386C (CY7C1386C / CY7C1387C) 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1386KV33 18-Mbit Pipelined DCD Sync SRAM
CY7C138 4K x 8/9 Dual-Port Static RAM
CY7C1380BV25 512K x 36 / 1 Mb x 18 Pipelined SRAM

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Not Recommended for New Design CY7C1386D CY7C1387D 18-Mbit (512K × 36/1M × 18) Pipelined DCD Sync SRAM 18-Mbit (512K × 36/1M × 18) Pipelined DCD Sync SRAM Features ■ Supports bus operation up to 200 MHz ■ Available speed grades are 200, and 167 MHz ■ Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ■ Depth expansion without wait state ■ 3.3 V core power supply (VDD) ■ 2.5 V or 3.