CY7C1386D Datasheet | Cypress

Not Remended for New Design CY7C1386D CY7C1387D 18-Mbit (512K × 36/1M × 18) Pipelined DCD Sync SRAM 18-Mbit (512K × 36/1M × 18) Pipelined DCD Sync SRAM Features - Supports bus operation up to 200 MHz - Available speed grades are 200, and 167 MHz - Registered inputs and outputs for pipelined operation - Optimal for performance (double-cycle deselect) - Depth expansion without wait state - 3.3 V core power supply (VDD) - 2.5 V or 3.3 V I/O power supply (VDDQ) - Fast clock-to-output times - 3 ns (for 200 MHz device) - Provides high performance 3-1-1-1 access rate - User selectable burst counter supporting Intel Pentium Interleaved or linear burst sequences - Separate processor and controller address strobes - Synchronous self-timed writes - Asynchronous output enable - CY7C1386D available in JEDEC-standard Pb-free 100-pin TQFP. CY7C1387D available in JEDEC-standard Pb-free 100-pin TQFP and non Pb-free 165-ball BGA package - IEEE 1149.1 JTAG-patible boundary scan - ZZ sleep mode option Functional Description The CY7C1386D/CY7C1387D SRAM integrates 512K × 36/1M × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BWX, and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self timed write cycle.This part supports byte write...