This datasheet includes multiple variants, all published together in a single manufacturer document.
| Part number | CY7C1423JV18 |
|---|---|
| Datasheet | CY7C1423JV18 CY7C1422JV18 Datasheet (PDF) |
| File Size | 705.88 KB |
| Manufacturer | Cypress (now Infineon) |
| Description | 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
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The DDR-II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations.
See all Cypress (now Infineon) datasheets
| Part Number | Description |
|---|---|
| CY7C1423AV18 | 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| CY7C1423BV18 | 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| CY7C1423KV18 | 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture |
| CY7C142 | 2K x 8 Dual-Port Static RAM |
| CY7C1420AV18 | (CY7C14xxAV18) 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1420BV18 | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1420JV18 | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1420KV18 | 36-Mbit DDR II SRAM Two-Word Burst Architecture |
| CY7C1421AV18 | 1.8V Synchronous Pipelined SRAM |
| CY7C1422AV18 | 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
