CY7C144 Datasheet | Cypress

Features - True Dual-Ported memory cells which allow simultaneous reads of the same memory location - 8K x 8 organization (CY7C144) - 8K x 9 organization (CY7C145) - 0.65-micron CMOS for optimum speed/power - High-speed access: 15ns - Low operating power: ICC = 160 m A (max.) - Fully asynchronous operation - Automatic power-down - TTL patible - Master/Slave select pin allows bus width expansion to 16/18 bits or more - Busy arbitration scheme provided - Semaphores included to permit software handshaking between ports - INT flag for port-to-port munication - Available in 68-pin PLCC, 64-pin and 80-pin TQFP Functional Description The CY7C144 and CY7C145 are high-speed CMOS 8K x 8 and 8K x 9 dual-port static RAMs. Various arbitration schemes are included on the CY7C144/5 to handle situations when multiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. The CY7C144/5 can be utilized as a standalone 64/72-Kbit dual-port static RAM or multiple devices can be bined in order to function as a 16/18-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, munications status buffering, and dual-port video/graphics memory. Each port has independent control pins: chip enable (CE), read or write enable (R/W), and output enable (OE). Two flags, BUSY and INT, are provided on each port. BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag (INT) permits munication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is prised of eight shared latches....