CY7C1473V25
Features
- No Bus Latency™ (No BL™) architecture eliminates dead cycles between write and read cycles.
- Can support up to 133-MHz bus operations with zero wait states
- Data is transferred on every clock
- Pin patible and functionally equivalent to ZBT™ devices
- Internally self-timed output buffer control to eliminate the need to use OE
- Registered inputs for flow-through operation
- Byte Write capability
- 2.5V/1.8V I/O power supply
- Fast clock-to-output times
- 6.5 ns (for 133-MHz device)
- 8.5 ns (for 100-MHz device)
- Clock Enable (CEN) pin to enable clock and suspend operation
- Synchronous self-timed writes
- Asynchronous Output Enable
- Offered in JEDEC-standard lead-free 100 TQFP, and 165-ball f BGA packages for CY7C1471V25 and CY7C1473V25. 209-ball f BGA package for CY7C1475V25.
- Three chip enables for simple depth expansion.
- Automatic Power-down feature available using ZZ mode or CE deselect.
- JTAG boundary scan for BGA and f BGA packages
- Burst Capability- linear or...
