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CY7C1510V18 - 1.8V Synchronous Pipelined SRAM

Key Features

  • Separate independent read and write data ports.
  • Supports concurrent transactions.
  • 250 MHz clock for high bandwidth.
  • 2-word burst on all accesses.
  • Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 500 MHz) at 250 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
  • Echo clocks (CQ and CQ) simp.

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Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C1510AV18 72-Mbit QDR-II SRAM 2-Word Burst Architecture
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 72-Mbit QDR™-II SRAM 2-Word Burst Architecture Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses ■ Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 500 MHz) at 250 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems ■ Single multiplexed address input bus latches address inputs for both read and write ports ■ Separate port selects for depth expansion ■ Synchronous internally self-timed writes ■ Availabl