CY7C1512KV18 - 72-Mbit QDR II SRAM Two-Word Burst Architecture

This page provides the datasheet information for the CY7C1512KV18, a member of the CY7C1525KV18 72-Mbit QDR II SRAM Two-Word Burst Architecture family.

Product Overview

Cypress Semiconductor

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Datasheet Details

Part number	CY7C1512KV18
Manufacturer	Cypress Semiconductor
File Size	620.47 KB
Description	72-Mbit QDR II SRAM Two-Word Burst Architecture
Datasheet	CY7C1512KV18 Datasheet
Additional preview pages of the CY7C1512KV18 datasheet.

CY7C1512KV18 Product details

Features

Separate independent read and write data ports.
Supports concurrent transactions.
350 MHz clock for high bandwidth.
Two-word burst on all accesses.
Double data rate (DDR) interfaces on both read and write ports (data transferred at 700 MHz) at 350 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
Echo clocks (CQ and CQ) sim.

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Published: Mar 14, 2017 |