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CY7C1518KV18

Manufacturer: Cypress (now Infineon)

CY7C1518KV18 datasheet preview

Datasheet Details

Part number	CY7C1518KV18
Datasheet	CY7C1518KV18-CypressSemiconductor.pdf
File Size	604.50 KB
Manufacturer	Cypress (now Infineon)
Description	72-Mbit DDR-II SRAM Two-Word Burst Architecture

CY7C1518KV18 Overview

CY7C1518KV18 CY7C1520KV18 72-Mbit DDR-II SRAM Two-Word Burst Architecture 72-Mbit DDR-II SRAM Two-Word Burst Architecture.

CY7C1518KV18 Key Features

72-Mbit density (4M × 18, 2M × 36)
333 MHz clock for high bandwidth
Two-word burst for reducing address bus frequency
Double data rate (DDR) interfaces (data transferred at
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
Echo clocks (CQ and CQ) simplify data capture in high speed
Synchronous internally self-timed writes
DDR II operates with 1.5 cycle read latency when DOFF is

More Datasheets from Cypress (now Infineon)

See all Cypress (now Infineon) datasheets

Part Number	Description
CY7C1518V18	1.8V Synchronous Pipelined SRAM
CY7C1510AV18	72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1510V18	1.8V Synchronous Pipelined SRAM
CY7C1511AV18	72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1511JV18	72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1511KV18	(CY7C15xxKV18) 72-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1511V18	(CY7C15xxV18) SRAM 4-Word Burst Architecture
CY7C1512	64K x 8 Static RAM
CY7C1512AV18	72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1512KV18	72-Mbit QDR II SRAM Two-Word Burst Architecture

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