CY7C1518KV18 Datasheet PDF (72-Mbit DDR-II SRAM Two-Word Burst Architecture) | Download Cypress Semiconductor CY7C1518KV18

CY7C1518KV18 - 72-Mbit DDR-II SRAM Two-Word Burst Architecture

Features

72-Mbit density (4M × 18, 2M × 36).
333 MHz clock for high bandwidth.
Two-word burst for reducing address bus frequency.
Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
Echo clocks (CQ and CQ) simplify data capture in high speed systems.
Synchronous in.

Datasheet Details

Part number	CY7C1518KV18
Manufacturer	Cypress
File Size	604.50 KB
Description	72-Mbit DDR-II SRAM Two-Word Burst Architecture
Datasheet	CY7C1518KV18 Datasheet
Additional preview pages of the CY7C1518KV18 datasheet.

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Full PDF Text Transcription

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CY7C1518KV18 CY7C1520KV18 72-Mbit DDR-II SRAM Two-Word Burst Architecture 72-Mbit DDR-II SRAM Two-Word Burst Architecture Features ■ 72-Mbit density (4M × 18, 2M × 36) ■ 333 MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high speed systems ■ Synchronous internally self-timed writes ■ DDR II operates with 1.5 cycle read latency when DOFF is asserted HIGH ■ Operates similar to DDR-I device with 1 cycle read latency when DOFF is asserted LOW ■ 1.

Published: Mar 14, 2017 |