CY7C1518KV18 Datasheet 72-mbit Ddr-ii Sram Two-word Burst Architecture

Manufacturer: Cypress (now Infineon)

Overview: CY7C1518KV18 CY7C1520KV18 72-Mbit DDR-II SRAM Two-Word Burst Architecture 72-Mbit DDR-II SRAM Two-Word Burst.

Datasheet Details

Part number	CY7C1518KV18
Manufacturer	Cypress (now Infineon)
File Size	604.50 KB
Description	72-Mbit DDR-II SRAM Two-Word Burst Architecture
Datasheet	CY7C1518KV18-CypressSemiconductor.pdf

Key Features

72-Mbit density (4M × 18, 2M × 36).
333 MHz clock for high bandwidth.
Two-word burst for reducing address bus frequency.
Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
Echo clocks (CQ and CQ) simplify data capture in high speed systems.
Synchronous in.

CY7C1518KV18 Distributor & Price

Compare CY7C1518KV18 distributor prices and check real-time stock availability from major suppliers. Prices and inventory may vary by region and order quantity.

More Datasheets from Cypress (now Infineon)

Part Number	Description
CY7C1518V18	1.8V Synchronous Pipelined SRAM
CY7C1510AV18	72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1510V18	1.8V Synchronous Pipelined SRAM
CY7C1511AV18	72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1511JV18	72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1511KV18	(CY7C15xxKV18) 72-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1511V18	(CY7C15xxV18) SRAM 4-Word Burst Architecture
CY7C1512	64K x 8 Static RAM
CY7C1512AV18	72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1512KV18	72-Mbit QDR II SRAM Two-Word Burst Architecture