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CY7C1524AV18 - 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

This page provides the datasheet information for the CY7C1524AV18, a member of the CY7C1522AV18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture family.

Description

The CY7C1522AV18, CY7C1529AV18, CY7C1523AV18, and CY7C1524AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate IO (DDR-II SIO) architecture.

The DDR-II SIO consists of two separate ports: the read port and the write port to access the memory array.

Features

  • Functional.

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Datasheet preview – CY7C1524AV18

Datasheet Details

Part number CY7C1524AV18
Manufacturer Cypress Semiconductor
File Size 735.55 KB
Description 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
Datasheet download datasheet CY7C1524AV18 Datasheet
Additional preview pages of the CY7C1524AV18 datasheet.

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Full PDF Text Transcription

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CY7C1522AV18, CY7C1529AV18 CY7C1523AV18, CY7C1524AV18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features ■ ■ ■ ■ ■ Functional Description The CY7C1522AV18, CY7C1529AV18, CY7C1523AV18, and CY7C1524AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate IO (DDR-II SIO) architecture. The DDR-II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR-II SIO has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common IO devices. Access to each port is accomplished through a common address bus.
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