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CY7C401 - (CY7C401 - CY7C404) 64 x 4 Cascadable FIFO / 64 x 5 Cascadable FIFO

General Description

The CY7C401 and CY7C403 are asynchronous first-in first-out (FIFOs) organized as 64 four-bit words.

Key Features

  • 64 x 4 (CY7C401 and CY7C403) 64 x 5 (CY7C402 and CY7C404) High-speed first-in first-out memory (FIFO).
  • Processed with high-speed CMOS for optimum speed/power.
  • 25-MHz data rates.
  • 50-ns bubble-through time.
  • 25 MHz.
  • Expandable in word width and/or length.
  • 5-volt power supply ± 10% tolerance, both commercial and military.
  • Independent asynchronous inputs and outputs.
  • TTL-compatible interface.
  • Output enable functi.

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Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C402 (CY7C401 - CY7C404) 64 x 4 Cascadable FIFO / 64 x 5 Cascadable FIFO
CY7C4021KV13 72-Mbit QDR-IV HP SRAM
CY7C403 (CY7C401 - CY7C404) 64 x 4 Cascadable FIFO / 64 x 5 Cascadable FIFO
CY7C404 (CY7C401 - CY7C404) 64 x 4 Cascadable FIFO / 64 x 5 Cascadable FIFO
CY7C4041KV13 72-Mbit QDR-IV HP SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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1CY 7C40 2 CY7C401/CY7C403 CY7C402/CY7C404 64 x 4 Cascadable FIFO 64 x 5 Cascadable FIFO Features • 64 x 4 (CY7C401 and CY7C403) 64 x 5 (CY7C402 and CY7C404) High-speed first-in first-out memory (FIFO) • Processed with high-speed CMOS for optimum speed/power • 25-MHz data rates • 50-ns bubble-through time—25 MHz • Expandable in word width and/or length • 5-volt power supply ± 10% tolerance, both commercial and military • Independent asynchronous inputs and outputs • TTL-compatible interface • Output enable function available on CY7C403 and CY7C404 • Capable of withstanding greater than 2001V electrostatic discharge • Pin compatible with MMI 67401A/67402A words. Both the CY7C403 and CY7C404 have an output enable (OE) function.