CY7C4231V Datasheet | Cypress

CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs Features - High-speed, low-power, first-in, first-out (FIFO) memories - 64 x 9 (CY7C4421V) - 256 x 9 (CY7C4201V) - 512 x 9 (CY7C4211V) - 1K x 9 (CY7C4221V) - 2K x 9 (CY7C4231V) - 4K x 9 (CY7C4241V) - 8K x 9 (CY7C4251V) - High-speed 66-MHz operation (15-ns read/write cycle time) - Low power (ICC = 20 m A) - 3.3V operation for low power consumption and easy integration into low-voltage systems - 5V-tolerant inputs VIH max= 5V - Fully asynchronous and simultaneous read and write operation - Empty, Full, and Programmable Almost Empty and Almost Full status flags - TTL patible - Output Enable (OE) pin - Independent read and write enable pins - Center power and ground pins for reduced noise - Width expansion capability - Space saving 32-pin 7 mm × 7 mm TQFP - 32-pin PLCC Functional Description The CY7C42X1V are high-speed, low-power, FIFO memories with clocked read and write interfaces. All are nine bits wide. Programmable Features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and munications buffering. These FIFOs have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a Free-Running Clock (WCLK) and two Write Enable pins (WEN1, WEN2/LD). When WEN1 is LOW and WEN2/LD is HIGH, data is written into the FIFO on the rising edge of the WCLK signal. While WEN1, WEN2/LD is held active, data is continually written into the FIFO on each WCLK cycle. The output port is controlled in a similar manner by a Free-Running Read Clock (RCLK) and two Read Enable Pins (REN1, REN2). In addition, the CY7C42X1V has an Output Enable Pin (OE). The Read (RCLK) and Write (WCLK) clocks may be tied together for single-clock operation or the two clocks may be run independently for...