CY7C4291 Datasheet | Cypress

CY7C4281 CY7C4291 64K/128K x 9 Deep Sync FIFOs Features - High-speed, low-power, first-in first-out (FIFO) memories - 64K × 9 (CY7C4281) - 128K × 9 (CY7C4291) - 0.5-micron CMOS for optimum speed/power - High-speed 100-MHz operation (10-ns read/write cycle times) - Low power - ICC= 40 m A - - - - - - - - - - - - ISB = 2 m A Fully asynchronous and simultaneous read and write operation Empty, Full, and programmable Almost Empty and Almost Full status flags TTL patible Output Enable (OE) pin Independent read and write enable pins Center power and ground pins for reduced noise Supports free-running 50% duty cycle clock inputs Width Expansion Capability 32-pin PLCC Pin-patible density upgrade to CY7C42X1 family Pin-patible density upgrade to IDT72201/11/21/31/41/51 D0 - 8 Functional Description The CY7C4281/91 are high-speed, low-power FIFO memories with clocked read and write interfaces. All are nine bits wide. The CY7C4281/91 are pin-patible to the CY7C42X1 Synchronous FIFO family. Programmable Features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and munications buffering. These FIFOs have nine-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock (WCLK) and two write-enable pins (WEN1, WEN2/LD). When WEN1 is LOW and WEN2/LD is HIGH, data is written into the FIFO on the rising edge of the WCLK signal. While WEN1, WEN2/LD is held active, data is continually written into the FIFO on each WCLK cycle. The output port is controlled in a similar manner by a free-running read clock (RCLK) and two read enable pins (REN1, REN2). In addition, the CY7C4281/91 has an output enable pin (OE). The read (RCLK) and write (WCLK) clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write...