CY7C68024 Datasheet | Cypress

Features - High-Speed (480 Mbps) or Full-Speed (12 Mbps) USB support - Both mon NAND page sizes supported - 512 bytes - Up to 1 Gbit capacity - 2K bytes - Up to 8 Gbit capacity - Eight chip enable pins - Up to eight NAND flash single device chips - Up to four NAND flash dual-device chips - Industry-standard ECC NAND flash correction - 1-bit error correction per 256 bytes - 2-bit error detection per 256 bytes - Industry-standard (Smart Media) Page Management for Wear Leveling Algorithm, Bad Block Handling, and Physical to Logical management - Supports 8-bit NAND flash interfaces - Supports 30 ns, 50 ns, and 100 ns NAND flash timing - plies with the USB Mass Storage Class Specification Revision 1.0 - CY7C68024 plies with the USB 2.0 Specification for Bus-Powered Devices (TID# 40460274) - 43 m A typical active current - Space-saving and Pb-free 56-pin QFN package (8 mm × 8 mm) - Support for board-level manufacturing test through USB interface - 3.3 V NAND flash operation - NAND flash power management support Functional Description The EZ-USB NX2LP (NX2LP) implements a USB 2.0 NAND Flash controller. This controller adheres to the Mass Storage Class Bulk-Only Transport Specification. The USB port of the NX2LP is connected to a host puter directly or through the downstream port of a USB hub. The Host software issues mands and data to the NX2LP and receives the status and data from the NX2LP using the standard USB protocol. The NX2LP supports industry-leading 8-bit NAND flash interfaces and both mon NAND page sizes of 512 and 2k bytes. Eight chip enable pins allow the NX2LP to be connected to up to eight single or four dual-device NAND flash chips. Certain NX2LP features are configurable, enabling the NX2LP to meet the needs of different design requirements. NX2LP Block Diagram 24 MHz Xtal Chip Reset PLL VBUS D+ D- USB 2.0 Xceiver EZ-USB NX2LP Internal Control Logic Control Write Protect LED2# LED1# NAND Control Signals Smart HS/ FS USB Engine Data NAND Flash...