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CY7C9536B - OC-48/STM-16 Framer

Datasheet Summary

Description

Including Multiplex Structure, Rates and Formats.” ANSI T1.105-1995.

7.

American National Standards Institute.

Payload Mappings.” ANSI T1.105.02

1998.

8.

Simpson, W.

Features

  • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated.
  • Complies with ITU-Standards G.707/Y.1322 and G.783[1,2] www. DataSheet4U. com.
  • PPP control packets optionally sent to host CPU interface.
  • MAC/layer 3 address look up and tagging.
  • Programmable A1A2 processing bypass in Rx direction with frame sync input.
  • Complete section overhead (SOH), line overhead (LOH), and path overhead (POH) processing.

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Datasheet Details

Part number CY7C9536B
Manufacturer Cypress Semiconductor
File Size 835.00 KB
Description OC-48/STM-16 Framer
Datasheet download datasheet CY7C9536B Datasheet
Additional preview pages of the CY7C9536B datasheet.

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Full PDF Text Transcription

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CONFIDENTIAL CY7C9536B OC-48/STM-16 Framer with VC - POSIC2GVC™ Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated • Complies with ITU-Standards G.707/Y.1322 and G.783[1,2] www.DataSheet4U.com • PPP control packets optionally sent to host CPU interface • MAC/layer 3 address look up and tagging.
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