CY8C6245 Datasheet | Cypress

PSo C 6 MCU: CY8C62x5 Datasheet PSo C 62 MCU General Description PSo C® 6 MCU is a high-performance, ultra-low-power and secured MCU platform, purpose-built for Io T applications. Based on the PSo C 6 MCU platform, this product line is a bination of a dual CPU microcontroller with low-power flash technology, digital programmable logic, high-performance analog-to-digital conversion and standard munication and timing peripherals. Features 32-bit Dual CPU Subsystem - 150-MHz Arm® Cortex®-M4F (CM4) CPU with single-cycle multiply, floating point, and memory protection unit (MPU) - 100-MHz Cortex-M0+ (CM0+) CPU with single-cycle multiply and MPU - User-selectable core logic operation at either 1.1 V or 0.9 V - Active CPU current slope with 1.1-V core operation - Cortex-M4: 40 µA/MHz - Cortex-M0+: 20 µA/MHz - Active CPU current slope with 0.9-V core operation - Cortex-M4: 22 µA/MHz - Cortex-M0+: 15 µA/MHz - Three DMA controllers Memory Subsystem - 512-KB application flash, 32-KB auxiliary flash (AUXflash), and 32-KB supervisory flash (SFlash); read-while-write (RWW) support. Two 8-KB flash caches, one for each CPU. - 256-KB SRAM with programmable power control and retention granularity - One-time-programmable (OTP) 1-Kb e Fuse array Low-Power 1.7-V to 3.6-V Operation - Six power modes for fine-grained power management - Deep Sleep mode current of 7 µA with 64-KB SRAM retention - On-chip DC-DC buck converter, <1 µA quiescent current - Backup domain with 64 bytes of memory and real-time clock Flexible Clocking Options - 8-MHz internal main oscillator (IMO) with ±2% accuracy - Ultra-low-power 32-k Hz internal low-speed oscillator (ILO) - On-chip crystal oscillators (16 to 35 MHz, and 32 k Hz) - Phase-locked loop (PLL) for multiplying clock frequencies - Frequency-locked loop (FLL) for multiplying IMO frequency - Integer and fractional peripheral clock dividers Quad-SPI (QSPI)/Serial Memory Interface (SMIF) - Execute-In-Place (XIP) from external quad SPI...