CYU01M16ZCC Datasheet | Cypress

PRELIMINARY CYU01M16ZCC Mo BL3™ 16-Mbit (1M x 16) Pseudo Static RAM Features - Wide voltage range: 2.2V- 3.6V - Access Time: 70 ns - Ultra-low active power - Typical active current: 3 m A @ f = 1 MHz - Typical active current: 18 m A @ f = fmax - Ultra low standby power - 16-word Page Mode - Automatic power-down when deselected - CMOS for optimum speed/power - Deep Sleep Mode - Offered in a Lead-Free 48-ball BGA Package - Operating Temperature: - 40°C to +85°C can be put into standby mode when deselected (CE HIGH or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). Writing to the device is acplished by taking Chip Enable (CE LOW) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). Reading from the device is acplished by taking Chip Enables (CE LOW) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. Refer to the truth table for a plete description of read and write modes. Deep Sleep Mode is enabled by driving ZZ LOW. See the Truth Table for a plete description of Read, Write, and Deep Sleep mode. Functional Description[1] The CYU01M16ZCC is a high-performance CMOS Pseudo Static RAM organized as 1M words by 16 bits that supports an asynchronous memory interface. This device Features advanced circuit design to...